1. Field
The following description relates to a semiconductor device and a fabricating method thereof, and to, for example, a semiconductor device in which contacts for a plurality of electrodes are arranged inside a trench in different directions, and to a method of fabricating such a semiconductor device.
2. Description of Related Art
A MOS transistor, such as a double diffused MOS transistor, is often used as a high voltage semiconductor device. In such a MOS transistor, a channel is generally formed in a horizontal direction to the surface of the substrate. However, according to the recent decrease in design rules for constructing semiconductor devices, increasing attentions are paid on a trench MOS transistor such as a high voltage MOS transistor having a vertical channel for their efficiency in high level integration. The trench MOS transistor is generally constructed to have a drain arranged on a rear surface of the substrate, a source arranged on an upper surface of the substrate, and a gate arranged within a trench formed into a surface of the substrate. The electric current generally flows in an upward and downward direction of the substrate along the sidewall of the trench.
FIG. 1 is a plan view of an active region and an edge region of a semiconductor device, and FIG. 2 is a cross-sectional view of the semiconductor of FIG. 1 along line I-I.
Referring to FIGS. 1 and 2, a semiconductor device is divided into an active region X and an edge region Y. The active region X includes a trench 100 and a trench transistor cell 101-1 and an active region interior contact 101, and the edge region Y includes a contact pattern to apply voltage to the electrodes. To be more specific, a first insulating layer 210 is formed on the substrate 200 with a source structure 220 formed on the first insulating layer 210, and a second insulating layer 230, a gate structure 240 and a third insulating layer 250 are formed thereabove. Contact holes 231, 251 are formed in the second and third insulating layers 230, 250, respectively.
Because of a wide overlapping area between the gate structure 240 and the source structure 220 on the edge region Y where the contact pattern is formed, the semiconductor device may deteriorate over time due to a current leakage between the gate and the source or the gate and the drain.